Analysis of a cascaded multilevel inverter with fault-tolerant control

Jesús Aguayo Alquicira¹, Abraham Claudio Sánchez², Luis Gerardo Vela Valdés³, Marco Antonio Rodríguez⁴, Rodolfo Amalio Vargas Méndez⁵

¹ Doctor and Master of Science in Electronic Engineering, Centro Nacional de Investigación y Desarrollo Tecnológico-CENIDET, México. Professor, Centro Nacional de Investigación y Desarrollo Tecnológico-CENIDET, México. jaguayo@cenidet.edu.mx.

² Master of Science in Electrical Engineering, Instituto Tecnológico de la Laguna, Mexico. Doctor of Science in Electrical Engineering, Nacional Politécnico de Grenoble, France. Professor, Centro Nacional de Investigación y Desarrollo Tecnológico-CENIDET. peabraha@cenidet.edu.mx.

³ Master of Science in Electrical Engineering, Instituto Tecnológico de la Laguna. PhD in Automatic Control, Universidad Henry Poincaré, France. Professor, Centro Nacional de Investigación y Desarrollo Tecnológico- CENIDET.velaluis@cenidet.edu.mx

⁴ Doctor and Master of Science in Electronic Engineering, Centro Nacional de Investigación y Desarrollo Tecnológico-CENIDET, Mexico. Professor, Universidad Autonoma del Carmen. marblanco73@hotmail.com

⁵ Master of Science in Electronic Engineering PhD Student, Centro Nacional de Investigación y Desarrollo Tecnológico-CENIDET. Amalio08e@cenidet.edu.mx.

ABSTRACT

Cascaded multilevel inverters are widely used in industry for speed control of induction motors and, even when the converters' operation is highly reliable, several faults can occur, leading to poor engine performance or even causing the whole system to stop. It is desirable to keep the system operational when a failure occurs, even when degraded, and implementing fault-tolerant systems are thus a good choice. This paper presents a general strategy for fault-tolerant control in a 7-level cascaded multilevel inverter (the faults are in semiconductor devices); the paper includes simulation and experimental results to validate the method.

Keywords: modulation, in-phase pulse width modulation (IPDPWM), fault-tolerance, cascaded multilevel inverter.

Received: October 21th 2010 Accepted: November 2nd 2011

Introduction

Multilevel inverter operation for medium voltage (2.3kV to 13.8kV) and high power (0.4MW to 40MW) applications offers interesting advantages with increased output voltage level, e.g. harmonic reduction, output filter elimination, dv/dt transient reduction during commutation, low EMI emissions by overvoltages and power loss reduction (Cortés et al., 2008). Diode-clamped, cascade and flying capacitors are the multilevel inverters most used in industry (Bin Wu 2006, JaeChu et al., 2006). However, the number of switches needed in the topology increases with the number of levels and, although the switches may be highly reliable, a system's fault probability will become increased (Mingyao et al., 2007; Lei Hu et al., 2005). An unbalanced voltage is generated when a fault occurs which can produce permanent damage to the load or complete system failure (Barriuso et al., 2009, Francois et al., 2002).

Related studies about fault-tolerant multilevel inverter have been focused on different techniques for obtaining a three-phase balanced output voltage (Mingyao et al., 2007; Lei Hu et al., 2005; Shengming et al., 2006; Sanmin et al., 2004). Xiaomin analysed a flying capacitor-based four-level inverter using the material redundancy technique (using extra components) (Xiaomin et al., 2004). Other work has analysed a three-level diode clamped multilevel inverter and also used extra components to tolerate faults (Edison et al., 2006; Gun-Tae et al., 2004); a cascade multilevel inverter with an additional leg and redundancy technique regarding change of pulse width modulation (PWM) when a fault occurs has also been described (Francois et al., 2002). Several authors (Sanminet al., 2006; Surinet al., 2006) have presented a cascade multilevel inverter and fault-tolerant technique used to change PWM modulation in semiconductor power devices, whilst others (Barriusoet al., 2009, Mingyao et al., 2007 and Lei Hu et al., 2005) have shown tolerant control for an asymmetric cascade multilevel inverter using material redundancy. Others works (De Lillo et al., 2010) have dealt with a fault-tolerant system for electrical machines, focusing on Aerospatiale applications and electric vehicle applications (Xiong et al., 2008).

This work has analysed a fault-tolerant seven-level cascade multilevel inverter (figure 1), based on system modularity for modifying the switches' operation sequence (PWM). It was focused on verifying the limits of the configuration simulating one and two cell failures, but maintaining balanced output voltage and low harmonic distortion according to the application's rated voltage.

Fault analysis

Several studies have dealt with power systems' fault analysis (Aguayo et al., 2004; Pérez et al., 2009; Quiroga 2009); applications typically have protection functions (Friedrich et al., 2003), e.g. passive protection could become activated according to fault time duration (Sun et al., 2010); ´passive protection can thus be turned off. Only two types of fault have been taken into account in semiconductor power devices (short and open circuit) which are described in the following section (Lu et al., 2009).

Open circuit fault type

This type of fault appears when a switch remains off (even when the gate signal has been turned on); this situation avoids energy transfer to the load (Figure 2 shows a diagram of this kind of fault). The failure probability of this type of fault is 18% regarding total converter faults. When a fault is produced in any converter cell, voltage level is lost (positive or negative) according to the failed switch. However, two voltage levels are lost regarding the failed cell once a failure has been isolated with the auxiliary switch. Figure 3 presents an example one this type of fault for t=0.055seg.

Short-circuit fault type

This type of fault is presented when a switch is turnedon and the complementary switch of an inverter leg or a short circuit in a DC power supply (Sun et al., 2010). Energy transfer to the load is thus not possible; the consequence is an overcurrent in the power supply and the corresponding transistors. Depending on fault time duration, system protection can be activated (the whole system may become shut down). The probability of this kind of fault is 15% of total converter failures (Aguayo et al., 2004). Similar to the above, two output voltage levels are lost (Figure 3). Different situations can produce both types of failure, probably due to faulty gate control modulation an internal fail-

Fault-tolerant scheme

Fault detection and isolation (FDI) analysis must done before implementing any system reconfiguration technique. Several methods can be used for FDI: sensing resistance, transformation of the output current and sensing V_CE (Edison et al., 2006). The actuator as sensor method (Aguayo et al., 2004; Rodríguez et al., 2009) is used in this work for fault detection through V_CE and V_GE.

In-phase pulse width modulation (IPDPWM) reconfiguration

This paper analyses the fault-tolerant technique in a cascade multilevel inverter without physical component replacement; this method involved the in-phase pulse width modulation (IPDPWM) technique (Lei Hu et al., 2005), assigning six phase carrier signals (triangles) at different voltage levels compared to a reference (sine wave) for determining the switching pattern. The signals generated from comparing them were assigned to the six pairs of switches (keeping symmetrical waveform).

The idea was to analyse modulation index limits and use the semiconductor power devices' symmetry for reconfiguration purposes; material redundancy (modification of components) is necessary for the fault-tolerant technique, in other words, the modulation software (gate signals) implies hardware reconfiguration (semiconductor power devices), but there is no material redundancy.

Reconfiguration for only one faulty cell

When any fault occurs (in a semiconductor power device) the switch to the corresponding cell must be isolated and stopped. For example, considered that cell A1 was faulty (see Figure 2), then the signals corresponding to the fault cell are those at the upper and lower ends (see Figure 4). The carrier signal must thus be modified (a sinusoidal signal in Figure 4) for a waveform to avoid carrying out the comparison and thus leave cell A1out of in English service. Figure 5 shows the waveform.

The other two cells (phase B and C) must compensate for the energy delivered by the faulty cell. Table I shows the expressions describing three-phase references in line cycle (60Hz) information (adapted from Lei Hu et al., 2005); this data shows the limits of the modulation index which is a function of the application. Figure 6 shows the references' waveforms described by these expressions; it can be seen that the modulation index in the other phases was forced to increase just when the faulty cell stopped transferring energy to the load.

It does not matter which cell has switch failure with this reconfiguration, provided that gate signals are properly reassigned since the carriers in the top and bottom cell are assigned to the fault.

So far, the solution has been presented with only one faulty cell; however the system can keep running with this method even if the fault is present in two-cell stage, as shown below.

Reconfiguration for a cell having two faults

In this case, when two cells are faulty (in the same phase), the reference waveform becomes modified and does not compare with the four corresponding carriers, so phase voltage now has only three levels (only one cell working). The other references should compensate for a longer period (Figure 6). Expressions describing waveforms for references based on modulation index limits are presented in Table 2.

Validation with simulation results

Figure 7 shows the three phase waveform; before and after that a failure occurred (at t = 0. 55 sec), having 0.8 modulation index value (M = 0.8), 60 Hz frequency (f_m= 60 Hz) for the reference and 3,600 Hz triangular waveform frequency value (f_c= 3600Hz). Figure 8 shows phase A voltage in the same conditions described above, showing degradation in two levels (a higher and a lower level) when the failure occurred.

Figure 9 shows that the line to line voltage (V_ab) involved a greater amount of levels due to voltage measurement between lines representing the combination of two phase voltages. Voltage level was maintained even when a fault occurred. An important part of three-phase systems is voltage balance between phases (especially when an induction motor is the load). Figure 10 shows the system vector diagram for verifying such voltage balance, having minimum degradation of phase A voltage (6% reduction), while the other phases were compensated for, so that line voltage remained unchanged (22% increase). In other words, the power remained constant because the energy which was not provided by the faulty phase was compensated for by the other phases (lacking faults).

So far, validation method results would be as expected, but occurring with two full bridges when only one was faulty. Figure 11 presents three phase signals, before and after the occurrence of two failures (two failures occurred at the same time and in different cells of only one phase). The voltage of phase A having a 4- level degradation regarding waveform without fault is also presented; in this case, output waveform was the classic case of a 3- level inverter converter (Figure 12).

Figure 13 shows line voltage V_ab. The diagram shows that introducing the fault led to degradation of 2 output voltage levels, in the same way that voltage became degraded. It is interesting to know whether a system still remains balanced, i.e. if energy failing to provide a phase with failure is compensated for by energy supplying other stages which are not faulty. Figure 14 shows the vector diagram of a system having strong voltage phase degradation (49% reduction), while the other phases compensated for it so that line voltages remained unchanged and the system was balanced 20% increase) to verify such pattern.

Experimental results

The system was simulated using an experimental platform involving a seven-level cascade multilevel inverter, using semiconductor power devices. Table 3 presents the experimental conditions.

Figures 15, 16 and 17 present the results regarding voltage between two lines and their respective phases during the operation of a system without any faults and when the fault occurred in a semiconductor power device in a phase A cell. As can be seen, the effect of loss of levels was only displayed during phase A and voltages between phases had no visible changes.

Figure 18 presents line voltage V_aband the THD profile. Third harmonics appear when a fault occurs in a cell whilst the amplitude of such harmonics increases when two cells are faulty. The increase in harmonics is about 1% for every cell having a faulty switch. Low order harmonics (3, 5, 7 and 11) increased by o.5% on average.

Conclusions

This work has presented a reconfiguration using IPDPWM which, although easy to implement, has the advantage of maintaining balanced line to line voltage even after a fault happens in a switch with one or two cells in a particular system. This is important regarding charges requiring operation with balanced line voltages, such as induction motors. The reconfiguration strategy allowed the system to become repaired without having to suspend operation. Simulation and experimental results have been shown for validating the method.

References

Aguayo, J., Claudio, A. Vela, L.G. Gentile, S., A survey of fault diagnosis methods for induction motors drives under inverter fault conditions., International Conference of Electrical and Electronics Engineering, (ICEEE). Acapulco Guerrero, México. June 2004, pp. 367 - 372

Barriuso, P., Dixon J., Flores, P., Morán, L., Fault tolerant reconfiguration system for asymmetric multilevel converters using bi -directional power switches., IEEE Trans. Ind. Electron, vol. 56, no. 4, pp. 1300-1306, March 2009.

Bin, W., High Power Converters and AC Drives., Wiley Inter-Science, Toronto Canada, 2006, pp. 80-87.

Cortés, C.A., Deprez, W., Driesen, J., Pérez, J.J., Determinación de pérdidas eléctricas en motores de inducción modelados electromagnéticamente con el método de los elementos finitos., Ingeniería e Investigación, Universidad Nacional de Colombia, Bogotá, Colombia. Vol. 28, Núm. 3, diciembre, 2008, pp. 64-74

Da Silva, E.R., Lima, W.S., de Oliveira Jr., A.S., Jacobina, C.B., Detection and compensation of switch faults in a three level inverter., Power Electronics Specialists Conference PESC'06, Jeju, Korea. June 2006, pp. 1309-1315.

De Lillo L., Empringham, L., Wheeler, P.W., Khwan-On, S., Gerada, C., Othman, M.N., Xiaoyan H., Multiphase power converter drive for fault-tolerant machine development in aerospace application., IEEE Trans. Ind. Electron., vol. 57, no. 2, pp. 575-583, Feb. 2010.

Francois, B., Hautier, J.P., Design of a fault tolerant control system for a NPC multilevel inverter., Volume 4, No. 8-11. 28^th Annual Conference of IEEE Industrial Electronics Conference (IECON). Sevilla, Spain. November 2002, pp. 1075-1080.

Fuchs, F.W., Some Diagnosis Methods for Voltage Source Inverters In Variable Speed Drives with Induction Machines A Survey., 29^th Annual Conference of IEEE Industrial Electronics Conference(IECON). Virginia, USA. Volume 2, Nov. 2003, pp. 1378 - 1385.

Gun-Tae, P., Tae-Jin, K., Dae-Wook, K., Dong-Seok, H., Control Method of NPC Inverter for Continuous Operation Under One Phase Fault Condition., Power Electronics Specialists Conference, PESC'04, Aachen, Germany. June 04, pp. 2188-2193

Jae-Chu, L., Tae-Jin, K., Dae-Wook, K., Dong-Seok, H., A Control Method for Improvement of Reliability in Fault Tolerant NPC Inverter System., Power Electronics Specialists Conference, PESC'06, Jeju, Korea. June 2006, pp. 1304-1308.

Khomfoi, S., Tolbert, L.M., A Reconfiguration Technique for Multilevel Inverters Incorporating a Diagnostic System Based on Neural Network., Computers in Power Electronics, COMPEL. Troy, New York, USA. July 2006, pp. 317-323.

Lei, H., Mingyao, M., Alian, C., Xiangning, H., Reconfiguration of Carrier-based Modulation Strategy for Fault Tolerant Multilevel Inverters., 31^th Annual Conference of IEEE Industrial Electronics Conference, IECON. Carolina, USA. Nov. 2005, pp. 1048-1053.

Lezana, P., Aguilera, R., Rodríguez, J., Fault detection on multi-cell converter based on output voltage frequency analysis., IEEE Trans. Ind. Electron., vol. 56, no. 6, pp. 2275-2283; June 2009.

Lu, B., Sharma, S., A literature review of IGBT fault diagnostic and protection methods for power inverters., IEEE Trans. Ind. Appl., vol. 45, no. 5, pp. 1770 - 1777. Sep./Oct. 2009.

Mingyao, M., Lei, H., Alian, C., Reconfiguration of Carrier-Based Modulation Strategy for Fault Tolerant Multilevel Inverters., IEEE Transactions on Power Electronics, vol. 22, No. 5, Sep. 2007, pp 2050-2060.

Pérez Hernández, L., Mora Flórez, J., Bedoya Cebayos, J., A linear approach to determining an SVM-basedfaultlocator'soptimalparameters., Ingeniería e Investigación, Universidad Nacional de Colombia, Bogotá, Colombia Vol. 29, Núm. 1, abril, 2009, pp. 76-8.

Quiroga, J. E., Detección de cortocircuito en el devanado de un motor sincrónico de imanes permanentes usando corriente de secuencia negativa en dominio tiempo., Ingeniería e Investigación, Universidad Nacional de Colombia, Bogotá, Colombia. Vol. 29, Núm. 2, agosto, 2009, pp. 48-52

Rodríguez, M. A., Claudio, A., Theillio, D., Vela, L.G., Hernández, L., Strategy to replace the damaged element for fault-tolerant induction motor drive., in Proc. IEEE Appl. Power Electron. Conf., Washington, DC, February 15-19, 2009, pp. 343-346.

Sanmin, W., Bin, W., Fahai, L., Xudong, S., Control Method for Cascade H-Bridge Multilevel Inverter with Faulty Power Cells., Applied Power Electronics Conference and Exposition, APEC. Miami Beach, Frorida, USA. Volume 1, No 9-13 Feb. 2003, pp. 261 - 267

Sanmin, W., Bin, W., Rizzo, S., Zargari, N., Comparison of control schemes for multilevel inverter with faulty cells., 30^th Annual Conference of IEEE Industrial Electronics Conference, IECON. Busan, Korea. Volume 1, No 2-6 Nov. 2004, pp. 1817 - 1822

Shengming, L., Longya, X., Strategies of Fault Tolerant Operation for Three-Level PWM Inverters., IEEE Trans. Power Electronics, Vol. 21, No. 4, July 2006, pp. 933-940.

Sun, Z., Wang, J., Howe, D., Jewell, G., Analytical prediction of short-circuit current in fault-tolerant permanent magnet machines., IEEE Trans. Ind. Electron., vol. 57, no. 99, pp. 1-1, 2010.

Xiaomin, K., Corzine, K.A., Familian, Y.L., A Unique Fault-Tolerant Design for Flying Capacitor Multilevel Inverter., IEEE Trans. Power Electronics, Vol. 19, No. 4, July 2004, pp. 979 -984.

Xiong, Y., Cheng, X., Shen, Z.J., Chunting, M., Hongjie, W., Garg, V.K., Prognostic and Warning System for Power-Electronic Modules in Electric, Hybrid Electric, and Fuel-Cell Vehicles., IEEE Trans. Ind. Electron., vol. 55, no. 6, pp. 2268 -2276, June 2008.

Zidani, F., Diallo, D., El Hachemi Benbouzid, M. and Naït-Saïd, R. A fuzzy-based approach for the diagnosis of fault modes in a voltage-fed PWM inverter induction motor drive., IEEE Trans. Ind. Electron., vol. 55, no. 2, pp. 586-593, Feb. 2008.