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Support vector machines implementation over integers modulo-M and Residue Number System
Implementación de máquinas de vectores de soporte sobre enteros módulo-M y en el Sistema Numérico de los Residuos
DOI:
https://doi.org/10.15446/dyna.v90n226.107112Palabras clave:
modular arithmetic; pattern recognition; Residue Number System (RNS); Support Vector Machines (SVN); digital signal processing; radial basis function (en)aritmética modular; reconocimiento de patrones; Sistema Numérico de los Residuos (SNR); Máquinas de Vectores de Soporte (MVS); procesamiento digital de señales; funciones de base radial (es)
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In low-power hardware implementations for classification algorithms, it is often essential to use physical resources efficiently. In this sense, the use of modulo-M integer operations instead of floating-point arithmetic, can lead to better performance, especially when M represents the dynamic range of an arithmetic block of the Residue Number System (RNS) [1,2]. Following this premise, this work is aiming to provide a methodology for implementing a classifier, specifically a Support Vector Machine (SVM) [3], using modulo-M integers and proposing a method for the use of Residue Number System.
En las implementaciones en hardware de baja potencia para algoritmos de clasificación, a menudo es esencial utilizar los recursos físicos de manera eficiente. En este sentido, la utilización de operaciones con enteros módulo-M en lugar de aritmética de punto flotante puede conducir a un mejor rendimiento, especialmente cuando M representa el rango dinámico de un bloque aritmético del Sistema Numérico de los Residuos (RNS) [1,2]. Siguiendo esta premisa, el objetivo de este trabajo es proporcionar una metodología para implementar un clasificador, en concreto, una Máquina de Vectores de Soporte (SVM) [3], utilizando enteros módulo-M y proponer un método para la utilización del Sistema Número de Residuos.
Referencias
Cardarilli, G.C., Nannarelli, A. and Re, M., Residue number system for low-power DSP applications, in: 2007 Conference Record of the Forty-First Asilomar Conference on Signals, Systems and Computers, 2007, pp. 1412-1416. DOI: https://doi.org/10.1109/ACSSC.2007.4487461
Albicocco, P., Cardarilli, G. C., Nannarelli A. and Re, M., Twenty years of research on RNS for DSP: Lessons learned and future perspectives, 2014 International Symposium on Integrated Circuits (ISIC), pp. 436-439, 2014. DOI: https://doi.org/10.1109/ISICIR.2014.7029575
Boser, B.E., Guyon, I.M. and Vapnik, V.N., A training algorithm for optimal margin classifiers, in: Proceedings of the fifth annual workshop on Computational learning theory, 1992, pp. 144-152. DOI: https://doi.org/10.1145/130385.130401
Cortes, C. and Vapnik, V., Support-vector networks, Machine learning, 1995, pp. 273-297. DOI: https://doi.org/10.1007/BF00994018
Chang, C.H., Molahosseini, A.S., Zarandi, A.A.E. and Tay, T.F., Residue number systems: a new paradigm to datapath optimization for low-power and high-performance digital signal processing applications., IEEE Circuits and Systems Magazine, 15, pp. 26-44, 2015. DOI: https://doi.org/10.1109/MCAS.2015.2484118
Arthireena, S. and Shanmugavadivel, G., Efficient sign detection using parallel prefix adder, in: IEEE International Conference on Electrical, Instrumentation and Communication Engineering (ICEICE), 2017, pp. 1-5. DOI: https://doi.org/10.1109/ICEICE.2017.8191852
Hakonen, M., Piitulainen, H. and Visala, A., Current state of digital signal processing in myoelectric interfaces and related applications, Biomedical Signal Processing and Control, 18, pp. 334-359, 2015. DOI: https://doi.org/10.1016/j.bspc.2015.02.009
Liao, L.Z., Tseng, Y.L., Chiang, H.H. and Wang, W.Y., EMG-based control scheme with SVM classifier for assistive robot arm, in: 2018 International Automatic Control Conference, 2018, pp. 1-5. DOI: https://doi.org/10.1109/CACS.2018.8606762
Tymchyshyn, V. and Khlevniuk A., Yet more simple SMO algorithm, 2020.
Shashua, A., Introduction to machine learning: class notes, in Introduction to machine learning: class notes, 2009, pp. 30-39.
Jenkins, W.K., Soderstrand, M.A. and Radhakrishnan, C., Historical patterns of emerging residue number system technologies during the evolution of computer engineering and digital signal processing, in: IEEE International Symposium on Circuits and Systems (ISCAS), pp. 2018, pp. 1-5. DOI: https://doi.org/10.1109/ISCAS.2018.8351066
Shoup, V., Congruences, in a computational introduction to number theory and algebra, Cambridge University Press, U.K., 2009, 15 P. DOI: https://doi.org/10.1017/CBO9781139165464
Salamat, S., Imani, M., Gupta, S. and Rosing, T., Rnsnet: in-memory neural network acceleration using residue number system, in: 2018 IEEE International Conference on Rebooting Computing (ICRC), 2018, pp. 1-12. DOI: https://doi.org/10.1109/ICRC.2018.8638592
Chervyakov, N.I., Lyakhov, P.A., Deryabin, M.A., Nagornov, N.N., Valueva, M.V. and Valuev, G.V., Residue number system-based solution for reducing the hardware cost of a convolutional neural network, Neurocomputing, 407, pp. 439-453, 2020. DOI: https://doi.org/10.1016/j.neucom.2020.04.018
Roohi, A., Taheri, M., Angizi, S. and Fan, D., Rnsim: efficient deep neural network accelerator using residue number systems. In: 2021 IEEE/ACM International Conference on Computer Aided Design, ICCAD, 2021, pp. 1-9, DOI: https://doi.org/10.1016/j.neucom.2020.04.018
Roohi, A., Angizi, S., Navaeilavasani, P, and Taheri, M., ReFACE: efficient design methodology for acceleration of digital filter implementations, in: 2022 23rd International Symposium on Quality Electronic Design (ISQED), 2022, pp. 1-6. DOI: https://doi.org/10.1109/ISQED54688.2022.9806144
Givaki, K., Khonsari, A., Gholamrezaei, M.H., Gorgin, S. and Najafi, M.H., A generalized residue number system design approach for ultra-low power arithmetic circuits based on deterministic bit-streams, in: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2023, 14 P. DOI: https://doi.org/10.1109/TCAD.2023.3250603
Ramírez, J., García, A., Meyer-Bäse, U., Taylor F. and Lloris, A., Implementation of RNS-based distributed arithmetic discrete wavelet transform architectures using field-programmable logic., Journal of VLSI Signal Processing Systems for Signal, Image and Video Technology, 33(1), pp. 171-190, 2003. [19] Nakahara, H. and Sasao, T., A deep convolutional neural network based on nested residue number system, in: 2015 25th International Conference on Field Programmable Logic and Applications (FPL), 2015, pp. 1-6. DOI: https://doi.org/10.1109/FPL.2015.7293933
Xu, W., You, X. and Zhang, C., Using Fermat number transform to accelerate convolutional neural network, in: 2017 IEEE 12th International Conference on ASIC (ASICON), 2017, pp. 1033-1036. DOI: https://doi.org/10.1109/ASICON.2017.8252655
Park, K.H. and Lee, S.W., Movement intention decoding based on deep learning for multiuser myoelectric interfaces, in: 2016 4th international winter conference on brain-computer Interface (BCI), 2016, pp. 1-2. DOI: https://doi.org/10.1109/IWW-BCI.2016.7457459
Lin, L.Y., Schroff, J., Lin, T P. and Huang, T.C., Residue number system design automation for neural network acceleration, in: IEEE International Conference on Consumer Electronics-Taiwan (ICCE-Taiwan), 2020, pp. 1-2. DOI: https://doi.org/10.1109/ICCE-Taiwan49838.2020.9258020
Sakellariou, V., Paliourasy, V., Kouretasy, I., Saleh, H. and Stouraitis, T., A High-performance RNS LSTM block, in: IEEE International Symposium on Circuits and Systems (ISCAS), 2022, pp. 1264-1268. DOI: https://doi.org/10.1109/ISCAS48785.2022.9937633
Sousa, L., Nonconventional computer arithmetic circuits, systems and applications, IEEE Circuits and Systems Magazine, 21(1), pp. 6-40, 2021. DOI: https://doi.org/10.1109/MCAS.2020.3027425
Samimi, N., Kamal, M., Afzali-Kusha, A. and Pedram, M., Res-DNN: a residue number system-based DNN accelerator unit., IEEE Transactions on Circuits and Systems I: regular papers, 67(2), pp. 658-671, 2019. DOI: https://doi.org/10.1109/TCSI.2019.2951083
Soloviev, R., Telpukhov, D., Mkrtchan, I., Kustov, A. and Stempkovskiy, A., Hardware implementation of convolutional neural networks based on residue number system, in: Moscow Workshop on Electronic and Networking Technologies (MWENT), 2020, pp. 1-7. DOI: https://doi.org/10.1109/MWENT47943.2020.9067498
Ran, S., Zhao, B., Dai, X., Cheng, C. and Zhang,Y., Software-hardware co-design for accelerating large-scale graph convolutional network inference on FPGA., Neurocomputing, 532, pp. 129-140, 2023. DOI: https://doi.org/10.1016/j.neucom.2023.02.032.
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1. Danny Alexandro Múnera-Ramírez, Diana Patricia Tobón-Vallejo, Martha Lucía Rodríguez-López. (2025). Anomaly classification in IIoT edge devices. Revista Facultad de Ingeniería Universidad de Antioquia, https://doi.org/10.17533/udea.redin.20250368.
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