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IMPLEMENTATION OF AN ALGORITHM FOR SQUARE ROOT COMPUTATION IN AN FPGA ARRAY BY USING FIXED POINT REPRESENTATION
IMPLEMENTACIÓN DEL ALGORITMO PARA EL CÁLCULO DE LA RAÍZ CUADRADA EN UN ARREGLO FPGA USANDO REPRESENTACIÓN DE PUNTO FIJO
Keywords:
VHDL, FPGA, Operation, Square root, VLSI (en)VHDL, FPGA, Operación, Raíz Cuadrada, VLSI (es)
The implementation of the square root computation in an FPGA device is presented in this work. The calculation is not one of convergence type, so the accuracy is very high and there are no conditions or restrictions for the operation to be fulfilled. It also consumes much less hardware surface than other algorithms for calculating the square root of a number. The number entered is of fixed-point representation, it is parameterizable, that is, two constants N and M can define the size of the number, where N defines the number of bits in the integer part of the number and M defines the number of bits of the fractional part.
En este trabajo se presenta la implementación de la raíz cuadrada de un número en un dispositivo FPGA. El algoritmo usado no es un algoritmo de convergencia, por tanto, la exactitud del cálculo es muy alta, además no existen restricciones de ningún tipo para que la operación sea llevada a cabo. El uso de hardware en la FPGA es mucho menor que el usado por otros algoritmos que también calculan la raíz cuadrada de un número. Para representar el número se usa la representación de punto fijo, para ello se usan dos parámetros, N y M, donde N define el número de bits que representan la parte entera y M define el número de bits de la parte fraccional. M y N son definidos en la síntesis del módulo.
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References
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