Published

2018-07-01

IMPLEMENTATION OF AN ALGORITHM FOR SQUARE ROOT COMPUTATION IN AN FPGA ARRAY BY USING FIXED POINT REPRESENTATION

IMPLEMENTACIÓN DEL ALGORITMO PARA EL CÁLCULO DE LA RAÍZ CUADRADA EN UN ARREGLO FPGA USANDO REPRESENTACIÓN DE PUNTO FIJO

DOI:

https://doi.org/10.15446/mo.n57.70377

Keywords:

VHDL, FPGA, Operation, Square root, VLSI (en)
VHDL, FPGA, Operación, Raíz Cuadrada, VLSI (es)

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Authors

  • Jorge H. López Group of Scientific Instrumentation and Microelectronics. Institute of Physics, University of Antioquia, A.A. 1226, Medellín, Colombia.
  • Johans Restrepo Group of Magnetism and Simulation. Institute of Physics, University of Antioquia, A.A. 1226, Medellín, Colombia.
  • Jorge E. Tobón Group of Solid State Physics. Institute of Physics, University of Antioquia, A.A. 1226, Medellín, Colombia

The implementation of the square root computation in an FPGA device is presented in this work. The calculation is not one of convergence type, so the accuracy is very high and there are no conditions or restrictions for the operation to be fulfilled. It also consumes much less hardware surface than other algorithms for calculating the square root of a number. The number entered is of fixed-point representation, it is parameterizable, that is, two constants N and M can define the size of the number, where N defines the number of bits in the integer part of the number and M defines the number of bits of the fractional part.

En este trabajo se presenta la implementación de la raíz cuadrada de un número en un dispositivo FPGA. El algoritmo usado no es un algoritmo de convergencia, por tanto, la exactitud del cálculo es muy alta, además no existen restricciones de ningún tipo para que la operación sea llevada a cabo.  El uso de hardware en la FPGA es mucho menor que el usado por otros algoritmos que también calculan la raíz cuadrada de un número. Para representar el número se usa la representación de punto fijo, para ello se usan dos parámetros, N y M, donde N define el número de bits que representan la parte entera y M define el número de bits de la parte fraccional. M y N son definidos en la síntesis del módulo.

References

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P. Soderquist and M. Leeser, IEEE Micro 17, 56 (1997).

E. Oberstar, Fixed-Point Representation and Fractional Math, Report Oberstar Consulting (Oberstar Consulting, 2007).

H. Kabuo, T. Taniguchi, A. Miyoshi, H. Yamashita, M. Urano, H. Edamatsu, and S. Kuninobu, IEEE Transactions on Computers 43, 43 (1994).

W. Chu and Y. Li, in Proceedings 5th Australasian Computer Architecture Conference. ACAC 2000 (Cat. No.PR00512) (2000) pp. 9-16.

K. Piromsopa, C. Aporntewan, and P. Chogsatitvataa, “An fpga implementation of a _xed-point square root operation” (2002).

How to Cite

APA

López, J. H., Restrepo, J. & Tobón, J. E. (2018). IMPLEMENTATION OF AN ALGORITHM FOR SQUARE ROOT COMPUTATION IN AN FPGA ARRAY BY USING FIXED POINT REPRESENTATION. MOMENTO, (57), 41–49. https://doi.org/10.15446/mo.n57.70377

ACM

[1]
López, J.H., Restrepo, J. and Tobón, J.E. 2018. IMPLEMENTATION OF AN ALGORITHM FOR SQUARE ROOT COMPUTATION IN AN FPGA ARRAY BY USING FIXED POINT REPRESENTATION. MOMENTO. 57 (Jul. 2018), 41–49. DOI:https://doi.org/10.15446/mo.n57.70377.

ACS

(1)
López, J. H.; Restrepo, J.; Tobón, J. E. IMPLEMENTATION OF AN ALGORITHM FOR SQUARE ROOT COMPUTATION IN AN FPGA ARRAY BY USING FIXED POINT REPRESENTATION. Momento 2018, 41-49.

ABNT

LÓPEZ, J. H.; RESTREPO, J.; TOBÓN, J. E. IMPLEMENTATION OF AN ALGORITHM FOR SQUARE ROOT COMPUTATION IN AN FPGA ARRAY BY USING FIXED POINT REPRESENTATION. MOMENTO, [S. l.], n. 57, p. 41–49, 2018. DOI: 10.15446/mo.n57.70377. Disponível em: https://revistas.unal.edu.co/index.php/momento/article/view/70377. Acesso em: 16 mar. 2026.

Chicago

López, Jorge H., Johans Restrepo, and Jorge E. Tobón. 2018. “IMPLEMENTATION OF AN ALGORITHM FOR SQUARE ROOT COMPUTATION IN AN FPGA ARRAY BY USING FIXED POINT REPRESENTATION”. MOMENTO, no. 57 (July):41-49. https://doi.org/10.15446/mo.n57.70377.

Harvard

López, J. H., Restrepo, J. and Tobón, J. E. (2018) “IMPLEMENTATION OF AN ALGORITHM FOR SQUARE ROOT COMPUTATION IN AN FPGA ARRAY BY USING FIXED POINT REPRESENTATION”, MOMENTO, (57), pp. 41–49. doi: 10.15446/mo.n57.70377.

IEEE

[1]
J. H. López, J. Restrepo, and J. E. Tobón, “IMPLEMENTATION OF AN ALGORITHM FOR SQUARE ROOT COMPUTATION IN AN FPGA ARRAY BY USING FIXED POINT REPRESENTATION”, Momento, no. 57, pp. 41–49, Jul. 2018.

MLA

López, J. H., J. Restrepo, and J. E. Tobón. “IMPLEMENTATION OF AN ALGORITHM FOR SQUARE ROOT COMPUTATION IN AN FPGA ARRAY BY USING FIXED POINT REPRESENTATION”. MOMENTO, no. 57, July 2018, pp. 41-49, doi:10.15446/mo.n57.70377.

Turabian

López, Jorge H., Johans Restrepo, and Jorge E. Tobón. “IMPLEMENTATION OF AN ALGORITHM FOR SQUARE ROOT COMPUTATION IN AN FPGA ARRAY BY USING FIXED POINT REPRESENTATION”. MOMENTO, no. 57 (July 1, 2018): 41–49. Accessed March 16, 2026. https://revistas.unal.edu.co/index.php/momento/article/view/70377.

Vancouver

1.
López JH, Restrepo J, Tobón JE. IMPLEMENTATION OF AN ALGORITHM FOR SQUARE ROOT COMPUTATION IN AN FPGA ARRAY BY USING FIXED POINT REPRESENTATION. Momento [Internet]. 2018 Jul. 1 [cited 2026 Mar. 16];(57):41-9. Available from: https://revistas.unal.edu.co/index.php/momento/article/view/70377

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CrossRef citations1

1. Mohammed Belhadj Mostefa, Abdelfettah Boussaid, Abdelmalek Khezzar. (2022). FPGA-based Algorithm for Harmonic Current Mitigation. 2022 2nd International Conference on Advanced Electrical Engineering (ICAEE). , p.1. https://doi.org/10.1109/ICAEE53772.2022.9962021.

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