Published

2010-01-01

The feasibility of speeding up 2D seismic migration using a specific processor on an FPGA

Viabilidad de acelerar la migración sísmica 2D usando un procesador específico implementado sobre un FPGA

Keywords:

data path optimisation, field programmable gate array (FPGA), hardware optimisation, Kirchhoff time migration (en)
optimización de camino de datos, FPGA, optimización de hardware, migración en tiempo de Kirchhoff (es)

Authors

  • Sergio Alberto Abreo Carrillo Universidad Industrial de Santander
  • Ana Beatriz Ramírez Silva Universidad Industrial de Santander

This paper was aimed at describing the state of the art regarding 2D migration from a software and hardware perspective. It also gives the current state of specific processing using field programmable gate array (FPGA) and then concludes with the feasibility of fully implementing 2D seismic migration on a FPGA via a specific processor. Work was used showing performance in different areas of knowledge to gain an overview of the current state of specific processing using FPGAs. As 2D seismic migration employs floating-point data, this article thus compiles several papers showing trends in floating-point operations in both general and specific processors. The information presented in this article led to concluding that FPGAs have a promising future in this area due to oil industry companies having begun to develop their own tools aimed at further optimising field exploration.

Este artículo describe el estado actual del proceso de migración 2D, desde el punto de vista del software y del hardware. Así mismo, presenta la actualidad del procesamiento específico usando FPGA, para luego poder concluir la viabilidad de implementar completamente el proceso de migración sísmica 2D sobre un FPGA a través de un procesador específico. Con el fin de obtener una visión global del estado actual del procesamiento específico usando FPGA, se usaron trabajos que muestran el desempeño de éste, en diversas áreas del conocimiento. Adicionalmente, como el proceso de migración sísmica 2D trabaja con datos en formato de punto flotante, en este artículo se presentan varios trabajos que muestran las tendencias en operaciones de punto flotante, tanto en procesadores de propósito general como específico; la información en él contenida permite concluir de manera general que los FPGA en esta área tienen un gran futuro, pues las empresas de la industria del petróleo han comenzado a desarrollar sus propias herramientas con el fin de optimizar aún más los procesos relacionados con la exploración de campos.

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References

Ach., Achronix Semiconductor Corporation, 2009. Disponible en: http://www.achronix.com/. Consultado Marzo de 2009.

Act., Actel Power Matters., 2009. Disponible en: http://www.actel.com/. Consultado Marzo de 2009.

Alt., Altera Corporation., 2009. Disponible en: http://www.altera.com/. Consultado Marzo de 2009.

Altera Corporation., Stratix IV Device Family Overview., 2008. Disponible en: http://www.altera.com/literature/hb/stratix-iv/stx4siv51001.pdf

Altera Corporation., Stratix III Device Family Overview., 2009. Disponible en: http://www.altera.com/literature/hb/stx3/stx3siii51001.pdf

Anghelescu, P., Ionita, S., Sofron, E., FPGA implementation of hybrid additive programmable cellular automata encryption algorithm, in HIS 08: Proceedings of the 2008 8th International Conference on Hybrid Intelligent, Systems, IEEE Computer Society, Washington, D.C., USA, 2008, pp. 96-101.

Anghelescu, P., Sofron, E., Rincu, C.-I., Lana, V.-G., Programmable cellular automata based encryption algorithm, Semiconductor Conference, CAS 2008, International 2, 2008, pp. 351-354.

Atm., Atmel Corporation., 2009. Disponible en: http://www.atmel.com/. Consultado Marzo de 2009.

Baker, Z. K., Prasanna, V. K., Time and area efficient pattern matching on fpgas, in FPGA 04: Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays, ACM, New York, N.Y., USA, 2004, pp. 223-232.

Beauchamp, M. J., Hauck, S., Underwood, K. D., Hemmert, K. S., Embedded floating-point units in FPGAs, in FPGA 06: Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays, ACM, New York, N.Y., USA, 2006, pp. 12-20.

Bogdán, I. A., Rivers, J., Beynon, R. J., Coca, D., High performance hardware implementation of a parallel database search engine for real-time peptide mass fingerprinting., Bioinformatics, 24(13), 2008, pp. 1498-1502.

Cho, Y. H., Mangione-Smith, W. H., Deep network packet filter design for reconfigurable devices., Trans. On Embedded Computing Sys., 7(2), 2008, pp. 1-26.

Cho, Y., Mangione-Smith, W., Fast reconfiguring deep packet filter for 1+ gigabit network., Field-Programmable Custom Computing Machines, FCCM 2005, 13th Annual IEEE Symposium, 2005, pp. 215-224.

Claerbout, J. F., Green, I., Basic Earth Imaging., Stanford University, 2008a, pp. 60-61.

Claerbout, J. F., Green, I., Basic Earth Imaging., Stanford University., 2008b., pp. 125-128.

Craven, S., Athanas, P., Examining the viability of FPGA supercomputing, EURASIP J. Embedded Syst., No. 1, 2007, pp. 13-13.

CWP., Center for wave phenomena colorado school of Mines., 2009. Disponible en: http://www.cwp.mines.edu/cwpcodes/. Consultado en marzo de 2009.

Dido, J., Geraudie, N., Loiseau, L., Payeur, O., Savaria, Y., Poirier, D., A flexible floating-point format for optimizing data-paths and operators in FPGA based DSPS, in FPGA 02: Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays, ACM, New York, N.Y., USA, 2002, pp. 50-55.

GEO., Geocluster Seismic Processing System., 2009. Disponible en: http://www.cggveritas.com/default.aspx?cid=13. Consultado Marzo de 2009.

He, C., Lu, M., Sun, C., Accelerating seismic migration using FPGA-based coprocessor platform, in FCCM 04: Proceedings of the 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, IEEE Computer Society, Washington, D.C., USA, 2004, pp. 207-216.

He, C., Sun, C., Lu, M., Zhao, W., Prestack Kirchhoff time migration on high performance reconfigurable computing platform, SEG Technical Program Expanded Abstracts, Vol. 24, No. 1, 2005, pp. 1902-1905. Disponible en: http://link.aip.org/link/?SGA/24/1902/1

Hoang, D. T., Lopresti, D. P., FPGA implementation of systolic sequence alignment., in International Workshop on Field Programmable Logic and Applications, 1993.

Jean, J., Liang, X., Drozd, B., Tomko, K., Accelerating an ir automatic target recognition application with FPGAs., in FCCM 99: Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines, IEEE Computer Society, Washington, D.C., USA, 1990, pp. 290.

Lat., Lattice Semiconductor Corporation., 2009. Disponible en: http//:www.latticesemi.com/. Consultado Marzo de 2009.

OME., Omega Seismic Processing System., 2009. Disponible en: http://www.westerngeco.com/content/services/dp/omega/index.aspx Consultado Marzo de 2009.

Panetta, J., de Souza Filho, P. R. P., da Cunha Filho, C. A., da Motta, F. M. R., Pinheiro, S. S., Junior, I. P., Rosa, A. L. R., Monnerat, L. R., Carneiro, L. T., de Albrecht, C. H. B., Computational characteristics of production seismic migration and its performance on novel processor architectures., in in Proceedings of the 19th International Symposium on Computer Architecture and High Performance Computing, IEEE Computer Society, 2007.

Patterson, C., High performance des encryption in virtex(tm) FPGAs using jbits(tm), in FCCM 00: Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines, IEEE Computer Society, Washington, D.C., USA, 2000, pp. 113.

PRO., ProMAX Seismic Processing Family, 2009. Disponible en: http://www.halliburton.com/ps/default.aspx?pageid=.862n&navid=221n&prodid=MSE::1055450737429153. Consultado Marzo de 2009.

Puttegowda, K., Worek, W., Pappas, P., Dandapani, A., Athanas, P., Dickerman, A., A run-time reconfigurable system for gene-sequence searching, in Proceedings of the 16th International Conference on VLSI Design, IEEE Computer Society, 2003, pp. 561-566.

Qui., Quicklogic., 2009. Disponible en: http://www.quicklogic.com/. Consultado Marzo de 2009.

SEI., Seisup Seismic Processing System., 2009. Disponible en: http://www.geocenter.com/seisup/seisup.html. Consultado Marzo de 2009.

Sinnappan, R., Hazelhurst, S., A reconfigurable approach to packet filtering, in FPL 01: Proceedings of the 11th International Conference on Field-Programmable Logic and Applications., Springer-Verlag, London, UK, 2001, pp. 638-642.

Sloan, J., High Performance Linux Clusters with OSCAR, Rocks, OpenMosix, and MPI (Nutshell Handbooks), OReilly Media, Inc., 2004. Disponible en: http://www.amazon.ca/exec/obidos/redirect?tag=citeulike09-20&path=ASIN/0596005709.

Tessier, R., Burleson, W., Reconfigurable computing for digital signal processing: A survey., Journal of VLSI Signal Processing, 28, 2001, pp. 7-27.

TSU., Tsunami development., 2009. Disponible en: http://www.tsunamidevelopment.com/prestacktimemig.php. Consultado Marzo de 2009.

Underwood, K., FPGAs vs. cpus: trends in peak floating-point performance., in FPGA 04: Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays, ACM, New York, N.Y., USA, 2004, pp. 171-180.

Underwood, K., Hemmert, K., Closing the gap: Cpu and fpga trends in sustainable floating-point blas performance., Field Programmable Custom Computing Machines, FCCM 2004. 12th Annual IEEE Symposium, 2004, pp. 219-228.

USP., Us patent 6,996,470, 2009. Disponible en: http://www.patentstorm.us/patents/6996470.html. Consultado Marzo de 2009.

Villasenor, J., Schoner, B., Chia, K.-N., Zapata, C., Kim, H. J., Jones, C., Lansing, S., Mangione-Smith, B., Configurable computing solutions for automatic target recognition., FPGAs for Custom Computing Machines, Proceedings IEEE Symposium, 2006, pp. 70-79.

Wang, Y., Shen, Y., Optimized fpga realization of digital matched filter in spread spectrum communication systems., in CITWORKSHOPS 08: Proceedings of the 2008 IEEE 8th International Conference on Computer and Information Technology Workshops, IEEE Computer Society, Washington, D.C., USA, 2008, pp. 173-176.

Xil., Xilinx website., 2009. Disponible en: http://www.xilinx.com/. Consultado Marzo de 2009.

Xilinx Inc., AccelDSP Synthesis Tool, User Guide., 2008a. Disponible en: http://www.xilinx.com/support/documentation/sw manuals/acceldsp user.pdf

Xilinx Inc., ChipScope Pro 10.1 Software and Cores, User Guide., v10.1 edn., 2008 b. Disponible en: http://www.xilinx.com/support/documentation/swmanuals/chipscopeproswcores101ug029.pdf

Xilinx Inc., EDK Concepts, tools, and Techniques., 2008c. Disponible en: http://www.xilinx.com/support/documentation/swmanuals/edkctt.pdf

Xilinx Inc., PlanAhead Tutorial Release 10.1., 2008d. Disponible en: http://www.xilinx.com/support/documentation/swmanuals/PlanAhead10-1Tutorial.pdf

Xilinx Inc., Xilinx ISE 10.1 Design Suite Software Manuals and Help - PDF Collection., 2008e. Disponible en: http://www.xilinx.com/itp/xilinx10/books/manuals.pdf

Xilinx Inc., Average ModelSim XE-III Simulation Performance Compared to ModelSim Altera Edition., 2009a. Disponible en: http://www.xilinx.com/ise/verification/mxedetails.html#compare

Xilinx Inc., System Generator for DSP Getting Started Guide, User Guide and Reference Guide., 2009b. Disponible en: http://www.xilinx.com/support/documentation/swmanuals/sysgenbklist.pdf

Xilinx Inc., Virtex-5 Family Overview., 2009c., Disponible en: http://www.xilinx.com/support/documentation/datasheets/ds100.pdf

Xilinx Inc., Virtex-6 Family Overview., 2009d. Disponible en: http://www.xilinx.com/publications/prodmktg/Virtex6Overview.pdf

Yamada, M., Nishihara, A., A high-speed fir digital filter with csd coefficients implemented on FPGA., in ASPDAC 01: Proceedings of the 2001 conference on Asia South Pacific design automation, ACM, New York, N.Y., USA, 2001, pp. 7-8.