Model-based implementation of self-configurable intellectual property modules for image histogram calculation in FPGAs
Implementación de módulos de Propiedad Intelectual modificables para el cálculo de histogramas en FPGA sobre un flujo de diseño basado en modelos
DOI:
https://doi.org/10.15446/ing.investig.v37n2.62328Keywords:
Digital image processing, histogram calculation, FPGA, xilinx system generator, MATLAB®/Simulink®, self-configuration. (en)Procesado Digital de imágenes, cálculo de histogramas, FPGA, sistema de generación Xilinx MATLAB®/Simulink®, configuración automática. (es)
References
Alsuwailem, A. M., & Alshebeili, S. A. (2005). A new approach for real-time histogram equalization using FPGA. In International Symposium on Intelligent Signal Processing and Communication Systems (pp. 397–400). Hong Kong: IEEE. http://doi.org/10.1109/ISPACS.2005.1595430
Bailey, D. G. (2011). Design for Embedded Image Processing on FPGAs (1st ed.). Solaris South Tower, Singapore: John Wiley & Sons (Asia) Pte Ltd. http://doi.org/10.1002/9780470828519
Barranco, F., Díaz, J., Gibaldi, A., Sabatini, S. P., & Ros, E. (2012). Vector disparity sensor with vergence control for active vision systems. Sensors, 12, 1771–1799. http://doi. org/10.3390/s120201771
Blair, C., Robertson, N. M., & Hume, D. (2013). Characterizing a Heterogeneous System for Person Detection in Video Using Histograms of Oriented Gradients: Power Versus Speed Versus Accuracy. IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 3(2), 236–247.
Cho, J. U., Jin, S. H., Pham, X. D., Kim, D., & Jeon, J. W. (2007). FPGA-Based Real-Time Visual Tracking System Using Adaptive Color Histograms. In IEEE International Conference on Robotics and Biomimetics (pp. 172–177). Sanya, China: IEEE. http://doi.org/10.1109/ROBIO.2007.4522155
Garcés-Socarrás, L. M., Cabrera Sarmiento, A. J., Sánchez-Solano, S., Brox Jiménez, P., Ieno, E., & Pimenta, T. C. (2016). Modificación automática de arquitecturas de módulos hardware de procesado de imágenes. Revista de Ingeniería Electrónica, Automática Y Comunicaciones, XXXVII( 3/2016), 21–33. Retrieved from http://rielac.cujae.edu. cu/index.php/rieac/article/view/406
Garcés-Socarrás, L. M., Sánchez-Solano, S., Brox Jiménez, P., & Cabrera Sarmiento, A. J. (2013). Library for model-based design of image processing algorithms on FPGAs. Revista de La Facultad de Ingeniería Universidad Antioquia, 1(68), 36–47.
González, R. C., & Woods, R. E. (2007). Digital Image Processing. (M. J. Horton, M. McDonald, A. Dworkin, W. Opaluch, S. Disanno, & R. Kernan, Eds.) (3rd ed.). Upper Saddle River, New Jersey, USA: Prentice Hall.
Gorgon, M., & Tadeusiewicz, R. (2000). Hardware-based image processing library for Virtex FPGA. Reconfigurable Technology: FPGAs for Computing and Applications II, 4212, 1–10. http://doi.org/10.1117/12.402510
Gu, Q., Noman, A. Al, Aoyama, T., Takaki, T., & Ishii, I. (2013). A Fast Color Tracking System with Automatic Exposure Control. In 7th International Conference on Information and Automation or Sustainability (pp. 1–6). Yinchuan, China: IEEE.
Hanumantharaju, M. C., Ravishankar, M., Rameshbabu, D. R., & Ramachandran, S. (2011). A novel FPGA implementation of adaptive color image enhancement based on HSV color space. In 3rd International Conference on Electronics Computer Technology (ICECT 2011), Kanyakumari (Vol. 2, pp. 160–163). Kanyakumari: IEEE. http://doi.org/10.1109/ ICECTECH.2011.5941676
Jamro, E., Wielgosz, M., & Wiatr, K. (2007). FPGA Implementaton of Strongly Parallel Histogram Equalization. In IEEE Design and Diagnostics of Electronic Circuits and Systems (pp. 1–6). Krakow: IEEE. http://doi.org/10.1109/ DDECS.2007.4295260
Kelly, C., Siddiqui, F. M., Bardak, B., & Woods, R. (2014). Histogram of Oriented Gradients front end processing: an FPGA Based Processor Approach. In IEEE Workshop on Signal Processing Systems (pp. 1–6). Belfast: IEEE. http:// doi.org/10.1109/SiPS.2014.6986093
Kokufuta, K., & Maruyama, T. (2010). Real-time processing of contrast limited adaptive histogram equalization on FPGA. In 20th International Conference on Field Programmable Logic and Applications (pp. 155–158). Milano, Italy: IEEE Computer Society. http://doi.org/10.1109/FPL.2010.37
Ma, X., Najjar, W. A., & Roy-Chowdhury, A. K. (2014). Evaluation and Acceleration of High-Throughput Fixed-Point Object Detection on FPGAs. IEEE Transactions on Circuits and Systems for Video Technology, 25(6), 1051–1062. http:// doi.org/10.1109/TCSVT.2014.2360030
Maggiani, L., Salvadori, C., Petracca, M., Pagano, P., & Saletti, R. (2014). Reconfigurable architecture for computing histograms in real-time tailored to FPGA-based Smart Camera. In IEEE 23rd International Symposium on Industrial Electronics (pp. 1042–1046). Istanbul: IEEE. http://doi. org/10.1109/ISIE.2014.6864756
Muller, S. (1995). A New Programmable VLSI Architecture for Histogram and Statistics Computation in Different Windows. In International Conference on Image Processing, Washington, DC (pp. 73–76). Washington, DC: IEEE. http:// doi.org/10.1109/ICIP.1995.529042
Popinchalk, S. (2008a). Advanced Masking Concepts. Retrieved November 18, 2014, from http://blogs.mathworks.com/seth/2008/08/05/advanced-masking-concepts/
Popinchalk, S. (2008b). Dynamic Mask Dialogs. Retrieved November 18, 2014, from http://blogs.mathworks.com/ seth/2008/08/13/dynamic-mask-dialogs/
Popinchalk, S. (2008c). Mask Initialization and Self-Modifying Blocks. Retrieved November 18, 2014, from http:// blogs.mathworks.com/seth/2008/08/21/mask-initialization- and-self-modifying-blocks/
Pulli, K., Baksheev, A., Kornyakov, K., & Eruhimov, V. (2012). Real-time computer vision with OpenCV. Communications of the ACM, 55(6), 61–69. http://doi. org/10.1145/2184319.2184337
Qasim, S. M., Abbasi, S. A., & Almashary, B. A. (2009). An overview of advanced FPGA architectures for optimized hardware realization of computation intensive algorithms. In International Multimedia, Signal Processing and Communication Technologies (pp. 300–303). Aligarh: IEEE. http://doi.org/10.1109/MSPCT.2009.5164235
Sangiovanni-Vincentelli, A. (2005). The tides of EDA. Design & Test of Computers, IEEE, 20(6), 59–75. Retrieved from http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber= 1246165
Shahbahrami, A., Hur, J. Y., Juurlink, B., & Wong, S. (2008). FPGA implementation of parallel histogram computation. In 2nd HiPEAC Workshop on Reconfigurable Computing (pp. 63–72). Göteborg, Sweden.
Xilinx. (2010). Spartan-6 FPGA Block RAM. Datasheet: User Guide. Datasheet, Xilinx Inc.
Dimensions
PlumX
Article abstract page views
Downloads
How to Cite
License
Copyright (c) 2017 Luis Manuel Garcés Socarrás, Daniel Alejandro Romero Ares, Alejandro José Cabrera Sarmiento, Santiago Sánchez Solano, Piedad Brox Jiménez

This work is licensed under a Creative Commons Attribution 4.0 International License.
The authors or holders of the copyright for each article hereby confer exclusive, limited and free authorization on the Universidad Nacional de Colombia's journal Ingeniería e Investigación concerning the aforementioned article which, once it has been evaluated and approved, will be submitted for publication, in line with the following items:
1. The version which has been corrected according to the evaluators' suggestions will be remitted and it will be made clear whether the aforementioned article is an unedited document regarding which the rights to be authorized are held and total responsibility will be assumed by the authors for the content of the work being submitted to Ingeniería e Investigación, the Universidad Nacional de Colombia and third-parties;
2. The authorization conferred on the journal will come into force from the date on which it is included in the respective volume and issue of Ingeniería e Investigación in the Open Journal Systems and on the journal's main page (https://revistas.unal.edu.co/index.php/ingeinv), as well as in different databases and indices in which the publication is indexed;
3. The authors authorize the Universidad Nacional de Colombia's journal Ingeniería e Investigación to publish the document in whatever required format (printed, digital, electronic or whatsoever known or yet to be discovered form) and authorize Ingeniería e Investigación to include the work in any indices and/or search engines deemed necessary for promoting its diffusion;
4. The authors accept that such authorization is given free of charge and they, therefore, waive any right to receive remuneration from the publication, distribution, public communication and any use whatsoever referred to in the terms of this authorization.










