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A fully integral, differential, high-speed, low-power consumption CMOS recovery clock circuit
Circuito de recuperación de reloj CMOS completamente integrable, diferencial, de alta velocidad y bajo consumo de potencia
DOI:
https://doi.org/10.15446/ing.investig.v27n3.14847Keywords:
clock recovery circuit, MCML logic, ring oscillator, PLL, VCO (en)circuito recuperador de reloj, lógica MCML, oscilador de anillo, PLL, VCO (es)
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The clock recovery circuit (CRC) plays a fundamental role in electronic information recovery systems (hard disks, DVD and CD read/writeable units) and baseband digital communication systems in recovering the clock signal contained in the received data. This signal is necessary for synchronising subsequent information processing. Nowadays, this task is difficult to achieve because of the data’s random nature and its high transfer rate. This paper presents the design of a high-performance integral CMOS technology clock recovery circuit (CRC) working at 1.2 Gbps and only consuming 17.4 mW using a 3.3V power supply. The circuit was fully differentially designed to obtain high performance. Circuit architecture was based on a conventional phase lock loop (PLL), current mode logic (MCML) and a novel two stage ring-based voltage controlled oscillator (VCO). The design used 0.35 µm CMOS AMS process parameters. Hspice simulation results proved the circuit’s high performance, achieving tracking in less than 300 ns.
En los sistemas electrónicos de recuperación de información (discos duros, unidades de lectura y escritura de DVD y CD, etc.), así como en las comunicaciones digitales en banda base, los circuitos de recuperación de reloj (CRC) juegan un papel fundamental, extrayendo la señal de reloj implícita en los datos recibidos, dicha señal es necesaria para sincronizar el procesamiento posterior de la información. En la actualidad esta tarea es difícil de lograr, no solo por la naturaleza aleatoria de los datos, sino por su alta velocidad de transferencia. En este artículo se presenta el diseño de un circuito de recuperación de reloj integrable en tecnología CMOS de alto desempeño, que opera a 1.2Gbps y consume únicamente 17.4mW de una fuente de 3.3V.
Las altas prestaciones se logran al realizar un diseño completamente diferencial, utilizando arquitectura PLL convencional, lógica en modo corriente, así como un novedoso oscilador controlado por voltaje (VCO) de anillo de solo dos etapas. El diseño fue realizado con parámetros de proceso CMOS AMS de 0.35µm. Los resultados de la simulación en Hspice comprueban el buen desempeño del circuito, logrando la adquisición en menos de 300ns.
References
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Copyright (c) 2007 Daniel Pacheco Bautista, Francisco Rubén Castillo Soria, Mónico Linares Aranda, Manuel Salim Maza
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